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NXP Semiconductors /LPC18xx /I2S0 /RXFIFO

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Interpret as RXFIFO

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2SRXFIFO

Description

I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.

Fields

I2SRXFIFO

8 x 32-bit transmit FIFO.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data